In the prior art, charge coupled devices are well known as data storage devices. The use of charge coupled devices is primarily in shift register type storage devices in which data is entered as a serial bit stream at one end of the shift register and read out as a serial bit stream at the output end of the shift register.
An important advance was the serial-parallel-serial charged coupled device shift register. Such a memory includes three essential portions. First, data is entered one bit at a time into a serial input register. Second, data is transferred in parallel from the serial input register into a parallel section. This has been referred to as one row of data in the parallel section. The parallel section typically includes many rows as this is where the bulk of the data is stored. Whereas data bits were initially inserted into the input serial register bit by bit, propagation through the parallel register is row by row. In reality, individual bits propagate along their respective channels which are customarily referred to as columns. These columns are orthogonal to the rows. Third, data is transferred out of the last row of the parallel section into the output serial register from where it is read out serially bit by bit. The output may then be transmitted to a utilization device and/or recirculated to the input of the input serial register for continuous data retention.
The foregoing generally described arrangement, aptly called serial-parallel-serial, has a number of advantages coupled with a number of inherent disadvantages. The advantages include storage density, low cost per bit of storage and reduced power consumption. A principal disadvantage, however, is that there is a long latency period because the order in which bits can be read out is always identical to the order in which bits were originally written in. Thus, if the utilization device requires data that was just written into the serial input register, the entire storage must be cycled before the information is available at the serial output register.
In order to make data more randomly accessible, conventional line-addressable storage arrays were developed. In a line-addressable array, data is inserted into and read out from a line of shift registers. For the sake of description, let these lines be in the same direction as the columns previously defined in the SPS structure. One possible implementation is that alternate columns propagate data in opposite directions resulting in continuous loops provided by each pair of columns. The line-addressable array includes many such loops operating in parallel. As the name implies, the line-addressable array has the flexibility to be read from any one of the columns or loops. Thus, the utilization device has immediate acess to the desired data (zero latency). However, this greatly improved speed of operation as compared to that of a serial-parallel-serial structure is achieved at the expense of a reduced bit density and greater power consumption, resulting in a higher cost per bit.
It is thus apparent that neither the serial-parallel-serial nor the line-addressable organizations provide the optimum desired operating conditions. That is, the high bit density and low cost of the serial-parallel-serial configuration must be sacrificed in order to obtain the operating speed of a line-addressable array. As will become more apparent from the following and more detailed description of the presently disclosed invention, the advantageous aspects of a serial-parallel-serial configuration are retained while the speed of operation of a line-addressable array is also provided.